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Dr. Sudhanshu Janwadkar

Dr. Sudhanshu Janwadkar

Assistant Professor , Electrical Electronics and Communication Engineering (EECE)

N/A

About

Dr. Sudhanshu Janwadkar is an Assistant Professor at Sharda University, specializing in VLSI System Design and Embedded Systems.  He earned his Ph.D. from Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat, where his doctoral research on ASIC development for portable biomedical devices culminated in a successful chip tape-out under the MietY funded SMDP-C2SD project. His research develops low-power digital architectures and VLSI signal processing systems, primarily for healthcare and IoT applications. His research work has resulted publications in leading SCI/Scopus-indexed journals and reputed international conferences, focusing on areas such as low-power digital signal processing architectures, Vedic mathematics-inspired computational techniques and power-performance-area optimization.

Prior to joining Sharda University, he held various academic positions at Nirma University, Ahmedabad; CK Peethawala College of Engineering & Technology, Surat; and SVNIT, Surat. He also brings over three years of industry experience from Capgemini India Pvt. Ltd. and Tata Consultancy Services Ltd.

Dr. Janwadkar is also actively engaged in the academic community through peer review and editorial activities, and his ongoing research pursues energy-efficient embedded solutions for next-generation portable and IoT devices.

Experience
  • 12 years (Industry: 3, Academics: 9)
Qualification
  • PhD
Research

  • Sudhanshu Janwadkar and Rasika Dhavse, “Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition”, Circuits, Systems, and Signal Processing, 2025.
  • Adit Varia and Sudhanshu Janwadkar, "Optimized Architecture for Wallace Multiplier using Hybrid Compressors for Precision Medical Image Processing on FPGAs" International Conference on Knowledge Driven Approaches in VLSI and RF Design (KeDAR- 2025), 2025.
  • Sujal Bhojani, Umang Fultariya, Sudhanshu Janwadkar, "Novel Iterative Non-restoring Algorithm for Square Root Computation on FPGAs", In: Kumar, P., Navaraj, W., Moreira, F. (eds) Advancements in VLSI Design, Microelectronics Devices and Circuits. SPIN 2025.
  • Sudhanshu Janwadkar and Rasika Dhavse, “ASIC Design of Power and Area-efficient Programmable FIR Filter using Optimized Urdhva-Tiryagbhyam Multiplier for Impedance Cardiography”, Microprocessors and Microsystems, Vol. 107, 105048, 2024.
  • Sudhanshu Janwadkar and Rasika Dhavse, “ASIC Implementation of ECG denoising FIR filter by using Hybrid Vedic–Wallace tree Multiplier”, International Journal of Circuit Theory and Applications, 2023.

Certifications

  • IEEE, ISVE

Area of Interest

  • VLSI and Embedded Systems Design